Currently, development of microelectronic industry prompts an increasingly progress of memory technology. An object of a memory industry is to improve an integration density and to reduce a production cost. A non-volatile memory has an advantage of maintaining data information without a power supply, and plays an important role in information storage.
RRAM is advantageous due to its high speed (<5 ns), low power consumption (<1V), high memory density, and easy integration etc. RRAM is a strong competitor of next generation of semiconductor memory. Such a memory device typically has a structure of Metal-Insulator-Metal (M-I-M), including a layer of a variable-resistance material between two metal electrodes.
FIG. 1 illustrates a top view of a basic structure of an RRAM array. FIG. 2 illustrates a cross-sectional view of a memory cell of the RRAM array alone line A-A′ in FIG. 1. The RRAM array may include RRAM devices 10 arranged in a plurality of rows and columns. Each of the RRAM devices 10 may include a stack of an isolation dielectric layer 101, a bottom electrode layer 102, a layer 103 of a variable-resistance material and a top electrode layer 104.
Typically, the variable-resistance material may be a transition metal oxide, such as HfO2, TiO2, ZrO2, NiO, ZnO, W2O5 etc. The variable-resistance material may exhibit two stable states, i.e. a high-resistance state and a low-resistance state, corresponding to digital “0” and “1” respectively.
The variable-resistance material changes between the states of different resistance values possibly due to a filament conductive channel formed inside an oxide film. Open/close of the filament conductive channel determines whether a memory cell is in the high-resistance state or in the low-resistance state.
A desired RRAM device 10 may be selectively accessed using word lines and bit lines (not shown) for reading, writing and erasing operations. Typically, change from the high-resistance state to the low-resistance state is referred to as a programming or SET operation, and change from the low-resistance state to the high-resistance state is referred to as an erasing or RESET operation.
If a previously-opened filament channel is spontaneously closed without being controlled or a previously-closed filament channel is spontaneously opened without being controlled when an external voltage is applied thereto, the resistive state of the memory cell will change spontaneously but not in a controlled manner. It causes failure of data stored in the RRAM device. The failure of the transition metal oxide RRAM device may be the failure in a high-resistance state (digital “0”), or the failure in a low-resistance state (digital “1”). The failure in the high-resistance state and in the low-resistance state may be collectively referred to as a “resistive state failure”.
Therefore, a method for testing data retention time of the RRAM device is desired for estimating performance of the RRAM device. However, there is still no clear research result in failure mechanism and model of the RRAM device. No a test method for the RRAM device has been proposed.